The invention relates to feedback sample-and-hold circuits. Sample-and-hold circuits are used for example, in electronic integrated circuits for delay functions and find application alone and in banks of stages for time domain filtering, such as in a transversal filter. The FIG. 1 illustrates a known arrangement of a number of sample-and-hold circuit stages interconnected as a bank to work in conjunction with a common operational amplifier A. Each of the N stages, shown enclosed by a broken line, includes a basic sample-and-hold circuit section and a switched feedback path connecting the output of the sample-and-hold circuit to the inverting input of the amplifier A. The sample-and-hold circuit sections each include a sampling switch S.sub.S, a holding capacitor C.sub.H, and a buffer B. The sampling switches S.sub.S are operated successively by pulses of a set of individually associated primary sampling switching pulse trains T.sub.S. The feedback sections include feedback enabling switches S.sub.F, which are operated successively by pulses of a second set of switching pulse trains T.sub.F so that the feedback for any particular stage is enabled during the entire sample-and-hold process of that stage. The details of the switching pulse electrical connections to the sampling switches S.sub.S and the feedback enabling switches S.sub.F are readily apparent to those skilled in the art and are not shown in the drawing in order to avoid crowding.
For understanding the general mode of operation of one of the stages it is useful to first assume that its sampling switch S.sub.S is in the conducting, closed condition, so that the signal output tracks the signal input. When the sampling switch S.sub.S is now opened, the output is held at a fixed hold value. If the switch S.sub.S is a perfect switch and the amplifier A and the buffer B are ideal, then the hold output will be precisely the same magnitude as the input which was present when the sampling switch S.sub.S was opened. The feedback loop in conjunction with the amplifier A reduces the effect of a voltage offset in the buffer B and in the sampling switch S.sub.S on the signal output. The sampling switch S.sub.S is generally an electronic switching device and is particularly well implemented by the use of one or more FET (field effect transistor) devices such as MOS (metal-oxide-semiconductor) transistors.
While MOS devices are particularly suitable for use as electronic switching devices, they are nevertheless not perfect. Because of coupling between the gate, source, and drain of the MOS device, unwanted error charge in the form of switching charge feedthrough is fed onto the holding capacitor C.sub.H after the MOS sampling switch S.sub.S is opened. At this time, since the sampling switch S.sub.S no longer conducts from source to drain, the operational amplifier A can no longer act to preserve the correct charge on the holding capacitor C.sub.H. As a result, there arises a hold voltage offset, the magnitude of which is determined by the amount of charge feedthrough from the sampling switch S.sub.S to the holding capacitor C.sub.H divided by the capacitance value of the holding capacitor C.sub.H. Since the capacitance magnitude of the holding capacitor C.sub.H limits the speed with which it can be charged, it is not possible to decrease the holding voltage offset by increasing at will the capacitance magnitude of the holding capacitor C.sub.H.
One known way of decreasing the hold voltage offset has been to provide a charge feedthrough compensation switch across the sampling switch S.sub.S. This is described, for example, in U.S. Pat. No. 4,308,468 issued Dec. 29, 1981 to Gaylord G. Olson. Such an approach significantly reduces the gross effects of the feedthrough charge for a particular switching device, but it does not deal with the effects of variations in feedthrough charge characteristics from one switching device to the next. Since in actual practice no two switches are identical, the feedthrough charge effect of each sampling switch S.sub.S is reduced by its associated compensation switch only to the extent that the feedthrough charge effects of both are identical. Thus, for a bank of feedback sample-and-hold circuits, the variations in the net charge feedthrough of the sampling switches S.sub.S and any compensating switches which may be connected across these still results in variations among the holding capacitor voltages, even when all the stages are sampling an identical signal. This produces a fixed pattern noise in a configuration in which the outputs of the sample-and-hold circuits are repeatedly sequentially sampled. This problem is discussed in relation to transversal filtering in, for example, "A Programmable Transversal Filter for Voice-Frequency Applications" by Sunter et al. in IEEE Journal of Solid-State Circuits, Vol. SC-16, No. 4, August 1981, pp. 367-371.